1. Field of the Invention
The embodiments of the invention generally relate to integrated circuits, and more particularly to providing latchup suppression in integrated circuits.
2. Description of the Related Art
As electronic components continue to become smaller along with the internal structures in integrated circuits, it is getting easier to either completely destroy or otherwise impair the electronic components from latchup. Latchup occurs when a pnpn structure transitions from a low current high voltage state to a high current low voltage state through a negative resistance region (i.e., forming an S-Type I-V (current/voltage) characteristic).
Latchup is typically understood as occurring within a pnpn structure, or silicon controlled rectifier (SCR) structure. It is possible for these pnpn structures to be intentionally designed, or even unintentionally formed between structures. Hence, latchup conditions can occur within peripheral circuits or internal circuits, within one circuit (intra-circuit) or between multiple circuits (inter-circuit).
Latchup is typically initiated by an equivalent circuit of a cross-coupled pnp and npn transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second device (“regenerative feedback”). These pnp and npn elements can be any diffusions or implanted regions of other circuit elements (e.g., P-channel MOSFETs (metal oxide semiconductor field effect transistors), n-channel MOSFETs, resistors, etc.) or actual pnp and npn bipolar transistors. In complimentary metal oxide semiconductor (CMOS) structures, the pnpn structure can be formed with a p-diffusion in a n-well, and a n-diffusion in a p-substrate (“parasitic pnpn”). In this case, the well and substrate regions are inherently involved in the latchup current exchange between regions in the device.
The condition for triggering a latchup is a function of the current gain of the pnp and npn transistors, and the resistance between the emitter and the base regions. This inherently involves the well and substrate regions. The likelihood or sensitivity of a particular pnpn structure to latchup is a function of spacing (e.g., base width of the npn and base width of the pnp), current gain of the transistors, substrate resistance and spacings, the well resistance and spacings, and isolation regions.
In internal circuits and peripheral circuitry, latchup in both is a concern. Latchup can also occur as a result of the interaction of an electrostatic discharge (ESD) device, the input/output (I/O) off-chip driver, and adjacent circuitry initiated in the substrate from the overshoot and undershoot phenomena. These factors can be generated by CMOS off-chip driver circuitry, receiver networks, and ESD devices. In CMOS I/O circuitry, undershoot and overshoot can lead to injection in the substrate. Hence, both a p-channel MOSFET and a n-channel MOSFET can lead to substrate injection. Simultaneous switching of circuitry where overshoot or undershoot injection occurs, leads to injection into the substrate which leads to both noise injection and latchup conditions. Supporting elements in these circuits, such as pass transistors, resistor elements, test functions, over voltage dielectric limiting circuitry, bleed resistors, keeper networks and other elements can be present leading to injection into the substrate. Moreover, ESD elements connected to the input pad can also lead to latchup. ESD elements that can lead to noise injection and latchup include MOSFETs, pnpn SCR ESD structures, p+/n-well diodes, n-well-to-substrate diodes, n+ diffusion diodes, and other ESD circuits. ESD circuits can also contribute to noise injection into the substrate and latchup.
In particular, an additional process can occur by the interaction of “activated” and “unactivated” elements in a gate-array environment. In an application specific integrated circuit (ASIC) environment, a “sea of gates” philosophy allows customization and personalization of circuit elements at a metallization level where the silicon shapes are predefined. Unused n-diffusion shapes are grounded, and unused p-diffusion shapes are connected to VDD. Unfortunately, this implementation can lead to latchup. As the substrate potential rises relative to the n-diffusion, all of the gate array elements forward bias. As the substrate potential lowers, the vertical pnp can be activated by the unused p-diffusion elements, the n-well, and the substrate. This can occur as a result of minority carrier injection in the wells and substrate regions.
In an ASIC gate array environment, it has been observed that as a negative pulse is injected into an input pad, ESD current discharge to the substrate flows outside of the I/O cell region, leading to “turn-on” of the adjacent gate array regions connected to the VSS and VDD rails, which often results in an increased likelihood of latchup, and leads to the failure of the latchup specification.
With the scaling of standard CMOS technology, the spacing of the p+/n+ region decreases leading to a lower trigger condition and the onset of CMOS latchup. With the scaling of the shallow trench isolation (STI) for aspect ratio, the vulnerability of CMOS technology to latchup has increased. Furthermore, vertical scaling of the wells, and lower n-well and p-well implant doses also has increased the lateral parasitic bipolar current gains, leading to lower latchup robustness.
With the transition from p+ substrates to low doped p− substrates, the latchup robustness has continued to decrease. With mixed signal applications and radio frequency (RF) chips, a higher concern for noise reduction has lead to the continued lowering of the substrate doping concentration. This continues to lead to lower latchup immunity in mixed signal applications and RF technologies.
FIG. 1 is a graphical illustration of I-V characteristics of a pnpn structure highlighting the points of transition. Latchup can occur from voltage or current pulses that occur on the power supply lines, such as VDD and VSS. Transient pulses on power rails (e.g., substrate or wells) can trigger latchup processes. Latchup can also occur from a stimulus to the well or substrate external to the region of a SCR (i.e., a thyristor) structure from minority carriers.
Latchup can be initiated from internal or external stimulus, and is known to occur from single event upsets (SEU), which can include terrestrial emissions from nuclear processes, and cosmic ray events, as well as events in space environments. Cosmic ray particles can include proton, and neutron, gamma events, as well as a number of particles that enter the earth atmosphere. Terrestrial emissions from radioactive events, such as alpha particles, and other radioactive decay emissions can also lead to latchup in semiconductors.
For military, surveillance, satellite, and other outer space applications, it is desirable to have a high tolerance to latchup. Latchup can lead to failure of space applications triggered by cosmic rays, heavy ions, and proton and neutron events. The higher the latchup margin in military and outer space applications, the higher the vulnerability to single even upset (SEU) initiated latchup. Therefore, due to the problems associated with latchup, it would be advantageous to have structures and methods that improve the latchup tolerance in base CMOS technology or mixed signal applications.